The present invention relates to an automatic logic designing for performing a logic design of a digital logic system by a computer and, more particularly, to a designing method and system of forming a detailed logic circuit expressed by a Boolean expression on the basis of the behavioral description specification of a computer.
In association with the enlargement of a logic scale of a computer, an automatic logic designing method has conventionally been proposed for the purpose of automatization of the computer logic design. There has been proposed a method whereby a behavioral description is used to more simply describe the logic specification of a logic circuit of a large scale and a logic is formed from the behavioral description of the computer.
The behavioral description as an input of a conventional automatic logic designing system is described in a format similar to that of a software program in accordance with a predetermined language specification. For example, according to a format shown in FIG. 5 of JP-A-2-253476, "Logic Synthesis Method", a method of separately describing a conditional description and a behavioral description by using keywords IF and THEN is used. According to such a format, although the contents shown by the keywords IF and THEN can be freely described, it is difficult to understand the corresponding relation between the IF-conditional description and the THEN-behavioral description which are different.
On the other hand, in case of designing a logic of a computer by inputting data in a table format, a truth table is used. The truth table describes a logic value by partitioning the conditional portion and the behavioral portion by a partition line. In the designing of software, there is a decision table or the like which has been proposed in the thesis "Table Driven System" disclosed in the collection of theses of Information Processing Society of Japan, the 29th National Conference, pages 91 to 92, 1984. In the decision table, the conditions and the corresponding behavior are described by using delimiter characters without using any keyword.
In case of forming a multilevel logic from the above behavioral description, there is used a method whereby a behavior which is expressed by the behavioral description is realized by a plurality of regular logics which have been prepared and registered in a library and several regular logics in which the number of gates is small and the delay time is short are selected and combined, thereby forming a logic. Such a method is shown in JP-A-2-253476, "Logical Synthesizing Method" mentioned before.
In case of constructing the multilevel logic from the above behavioral description, a circuit in which the delay time is short and the number of gates is small can be realized by constructing the multilevel logic in consideration of the input polarity and output polarity of the gates constructing a logic circuit. For example, according to JP-A-64-91243, "Logic Gate Equivalent Converting Method", there has been proposed a method whereby by using a fact that a serial structure of an NAND gate and an inverter and a serial structure of an inverter and an NOR gate are equivalent, the inverter is moved in a logic circuit, and in the case where the inverters continuously appear, those inverters are deleted.
In case of using the conventional input description in the automatic logic designing system which realizes the above conventional automatic logic designing method, degrees of freedom on the description of the conditional description and behavioral description using the IF and THEN keywords are large. Therefore, it is difficult to correspond among different conditions. It is not easy to discriminate whether all of the conditions are satisfied or not. As the conditions and behaviors become complicated, the above obstacle becomes remarkable. On the other hand, since the contents of the description in the truth table are based on only the logic value of 0 or 1, the table size is large for the description of the complicated logic of a large scale and it is not easy to form such a truth table. In other words, according to the above conventional technique, an advanced table description which describes complicated conditions and behavior is difficult.
In case of forming a logic circuit on the basis of the above input description, on the other hand, when the conditional and behavioral equations are complicated, it is hard to obtain a logic circuit in which the number of gates and the delay time are set to the optimum values so long as the limited number of regular logics registered in the library. On the other hand, there has conventionally been used a method whereby a target logic circuit which has once been constructed by regular logics is developed into a two-level logic and is again synthesized to a multilevel logic. According to such a method, however, since a processing time increases with an increase in scale of the target logic, the conventional technique can be applied to only a logic of a small scale.
In the above conventional technique, the polarity upon formation of the multilevel logic has been considered for only a gate logic. However, a method of constructing a multilevel logic in which the polarity is considered is not yet proposed for a logic circuit having a more macro function whose abstraction degree is higher than that of a gate logic. With respect to a logic drawing corresponding to a design logic circuit, consideration has been made with respect to a good-looking about an arrangement and wirings of logic devices, no consideration is paid to the signal names which assist the understanding of the designed logic circuits.